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Preliminary W24256 32K x 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24256 is a normal speed, very low power CMOS static RAM organized as 32768 x 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbond's high performance CMOS technology.
FEATURES
*
Low power consumption: * Access time: 70 nS (max.) * Active :300 mW Standby :250 W * Single 5V power supply * Fully static operation * All inputs and outputs directly TTL compatible
* * * *
Three-state outputs Battery back-up operation capability Data retention voltage: 2V (min.) Packaged in 28-pin 600 mil DIP, 330 mil SOP and standard type one TSOP (8 mm x 13.4 mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN. A12 A14 A2 R O W D E C O D E R PRECHARGE CKT.
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28-pin DIP
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
A3 A4 A5 A6 A7 A13 I/O1 I/O8
CORE CELL ARRAY 512 ROWS 64 X 8 COLUMNS
DATA CNTRL. CLK GEN.
I/O CKT. COLUMN DECODER
WE CS OE
A11 A10 A1 A0 A8 A9
PIN DESCRIPTION
OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
SYMBOL A0-A14 I/O1-I/O8 CS
WE
28-pin TSOP
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Select Input Write Enable Input Output Enable Input Power Supply Ground
OE VDD VSS
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Publication Release Date: October 1999 Revision A1
Preliminary W24256
TRUTH TABLE
CS H L L L OE X H L X WE X H H L MODE Not Selected Output Disable Read Write I/O1-I/O8 High Z High Z Data Out Data In VDD CURRENT ISB, ISB1 IDD IDD IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Supply Voltage to VSS Potential Input/Output to VSS Potential Allowable Power Dissipation Storage Temperature Operating Temperature RATING -0.5 to +7.0 -0.5 to VDD +0.5 1.0 -65 to +150 0 to 70 UNIT V V W C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
Operating Characteristics
(VDD = 5V 10%; VSS = 0V; TA = 0 C to 70 C)
PARAMETER Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current
SYM. VIL VIH ILI ILO
TEST CONDITIONS VIN = VSS to VDD VI/O = VSS to VDD, CS = VIH (min.) or OE = VIH (min.) or
WE = VIL (max.)
MIN. -0.5 +2.2 -5 -5
TYP.* -
MAX. +0.8 VDD +1 +5 +5
UNIT V V A A
Output Low Voltage Output High Voltage Operating Power Supply Current Standby Power Supply Current
VOL VOH IDD ISB ISB1
IOL = +2.1 mA IOH = -1.0 mA
CS = VIL (max.), I/O = 0 mA , Cycle = min , Duty = 100 %
2.4 -
-
0.4 60 3 100 50
V V mA mA A A
CS = VIH (min.), Cycle = min. Duty = 100% CS VDD -0.2V L LL
Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 5V.
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Preliminary W24256
CAPACITANCE
(VDD = 5V, TA = 25 C, f = 1 MHz)
PARAMETER Input Capacitance Input/Output Capacitance
SYM. CIN CI/O
CONDITIONS VIN = 0V VOUT = 0V
MAX. 6 8
UNIT pF pF
Note: These parameters are sampled but not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load 0V to 3.0V 5 nS 1.5V See the drawing below CONDITIONS
AC TEST LOADS AND WAVEFORM
1 TTL OUTPUT 100 pF Including Jig and Scope OUTPUT
1 TTL
5 pF Including Jig and Scope (For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW )
3.0V 0V 5 nS
90% 10%
90% 10% 5 nS
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Publication Release Date: October 1999 Revision A1
Preliminary W24256
AC Characteristics, continued (VDD = 5V 10%; VSS = 0V; TA = 0 C to 70 C)
Read Cycle
PARAMETER SYM. W24256-70L/LL MIN. Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z Output Hold from Address Change
These parameters are sampled but not 100% tested
UNIT
MAX. 70 70 30 20 20 nS nS nS nS nS nS nS nS nS
TRC TAA TACS TAOE TCLZ* TOLZ* TCHZ* TOHZ* TOH
70 5 5 3
Write Cycle
PARAMETER SYM. W24256-70L/LL MIN. Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Data Valid to End of Write Data Hold from End of Write Write to Output in High Z Output Disable to Output in High Z Output Active from End of Write These parameters are sampled but not 100% tested CS, WE TWC TCW TAW TAS TWP TWR TDW TDH TWHZ* TOHZ* TOW 70 70 70 0 50 0 30 0 5 MAX. 25 30 nS nS nS nS nS nS nS nS nS nS nS UNIT
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Preliminary W24256
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC Address TOH DOUT TAA TOH
Read Cycle 2
(Chip Select Controlled)
CS TACS TCHZ TCLZ DOUT
Read Cycle 3
(Output Enable Controlled)
T RC Address TAA OE TAOE TOLZ CS TACS D OUT TCLZ T CHZ TOHZ TOH
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Publication Release Date: October 1999 Revision A1
Preliminary W24256
Timing Waveforms, continued
Write Cycle 1
TWC Address T WR OE
TCW CS T AW WE TAS TOHZ D OUT T DW D IN TDH (1, 4) T WP
Write Cycle 2 (OE = VIL Fixed)
T WC Address TCW CS TAW WE TAS TWP TWHZ (1, 4) TOH (2) TOW (3) TWR
D OUT
TDW DIN
TDH
Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied. 2. The data output from DOUT are the same as the data written to DIN during the write cycle. 3. DOUT provides the read data for the next address. 4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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Preliminary W24256
DATA RETENTION CHARACTERISTICS
(TA = 0 C to 70 C)
PARAMETER VDD for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time * Read Cycle Time
SYM. VDR IDDDR TCDR TR
TEST CONDITIONS CS VDD -0.2V CS VDD -0.2V, VDD = 3V See data retention waveform
MIN. 2.0 0 TRC*
TYP. -
MAX. 5.5 20 -
UNIT V A nS nS
DATA RETENTION WAVEFORM
VDD
0.9 V DD TCDR
VDR > 2V =
0.9 V DD TR
CS
VIH
CS > V DD - 0.2V =
VIH
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) 70 70 70 70 70 70 OPERATING CURRENT MAX. (mA) 60 60 60 60 60 60 STANDBY CURRENT MAX. (A) 100 50 100 50 100 50 PACKAGE
W24256-70L W24256-70LL W24256S-70L W24256S-70LL W24256Q-70L W24256Q-70LL
600 mil DIP 600 mil DIP 330 mil SOP 330 mil SOP Standard type one TSOP Standard type one TSOP
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
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Publication Release Date: October 1999 Revision A1
Preliminary W24256
PACKAGE DIMENSIONS
28-pin P-DIP
Dimension in Inches
Dimension in mm
Symbol
Min. Nom. Max.
0.210 0.010 0.150 0.016 0.058 0.008 0.155 0.018 0.060 0.010 1.460 0.590 0.540 0.090 0.120 0 0.630 0.650 0.600 0.545 0.100 0.130 0.160 0.022 0.064 0.014 1.470 0.610 0.550 0.110 0.140 15 0.670 0.090
Min. Nom. Max.
5.33 0.25 3.81 0.41 1.47 0.20 3.94 0.46 1.52 0.25 37.08 14.99 13.72 2.29 3.05 0 16.00 16.51 15.24 13.84 2.54 3.30 4.06 0.56 1.63 0.36 37.34 15.49 13.97 2.79 3.56 15 17.02 2.29
D
28 15
A A1 A2 B B1 c D E E1 e1 L
a
E1
eA S Notes:
1 14
S
E c
A A2
A1
Base Plane Seating Plane
L B B1
e1
a
eA
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimensions D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. . 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
28-pin SOP Wide Body
Symbol
Dimension in Inches
0.112 0.004 0.093 0.014 0.008 0.098 0.016 0.010 0.713 0.326 0.044 0.453 0.028 0.059 0.331 0.050 0.465 0.036 0.067 0.103 0.020 0.014 0.733 0.336 0.056 0.477 0.044 0.075 0.047 0.004 0 10
Dimension in mm
2.85 0.10 2.36 0.36 0.20 2.49 0.41 0.25 18.11 8.28 1.12 11.51 0.71 1.50 8.41 1.27 11.81 0.91 1.70 2.62 0.51 0.36 18.62 8.53 1.42 12.12 1.12 1.91 1.19 0.10 0 10
Min. Nom. Max. Min. Nom. Max.
28
15
e1
E HE
L
Detail F
1 b 14
A A1 A2 b c D E e HE L LE S y Notes:
D
e1 c
A2 A
S
e
y
A1
LE
Seating Plane
See Detail F
1. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension b does not include dambar protrusion/intrusion. 3. Dimensions D & E include mold mismatch . and determined at the mold parting line. 4. Controlling dimension: Inches. 5. General appearance spec should be based on final visual inspection spec.
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Preliminary W24256
Package Dimensions, continued
28-pin Standard Type One TSOP
HD
Symbol
Dimension In Inches Min. Nom. Max.
0.047 0.002 0.035 0.007 0.004 0.461 0.311 0.520 0.020 0.040 0.008 0.006 0.465 0.315 0.528 0.022 0.024 0.010 0.000 0 3 0.004 5 0.028 0.006 0.041 0.011 0.008 0.469 0.319 0.536
Dimension In mm Min. Nom. Max.
1.20 0.05 0.95 0.17 0.10 11.70 7.90 13.20 0.50 1.00 0.20 0.15 11.80 8.00 13.40 0.55 0.60 0.25 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21 11.90 8.10 13.60
D c
1
e
E
b
A2 A
A A1 A2 b c D E HD e L L1 Y Y
L L1
A1
Controlling dimension: Millimeters
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Publication Release Date: October 1999 Revision A1
Preliminary W24256
VERSION HISTORY
VERSION A1 DATE Oct. 1999 PAGE Initial issued DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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